For the circuit shown in the following figure I0-I3 are inputs to the 4:1 multiplexer R(MSB) and S are control bitsThe output Z can be represented by

PQ + PQ S + Q R S
 
P Q + PQ R + P Q S
 
P Q R + P QR + PQRS + Q R S
 
PQ R + PQR S + P Q R S + Q R S
 

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