Select topics and difficulty and just practice mcqs.
User (name or email)
pick difficulty level
number of questions
Let's practice 30 mcqs on
mcqs by everyone
A modulus-10 counter must have ________
The given circuit represents a(n) ________
synchronous BCD decade counter
four-bit binary counter
asynchronous BCD decade counter
Synchronous (parallel) counters eliminate the delay problems encountered with asynchronous (ripple) counters because the
input clock pulses are applied simultaneously to each stage.
input clock pulses are applied only to the last stage.
input clock pulses are not used to activate any of the counter stages.
input clock pulses are applied only to the first and last stages.
Many parallel counters use ________ presetting whereby the counter is preset on the active transition of the same clock signal that is used for counting
Select the response that best describes the use of the Master Reset on typical 4-bit binary counters
To enable the count mode, MR1 and MR2 must be held LOW.
When MR1 and MR2 are both HIGH, all Qs will be reset to zero.
When MR1 and MR2 are both HIGH, all Qs will be reset to one.
MR1 and MR2 are provided to synchronously reset all four flip-flops.
Modulus refers to ________
the maximum number of states in a counter sequence
the modulus of elasticity, or the ability of a circuit to be stretched from one mode to another
a method used to fabricate decade counter units
an input on a counter that is used to set the counter state, such as UP/DOWN
A 5-bit asynchronous binary counter is made up of five flip-flops, each with a 12 ns propagationdelay.
The total propagation delay (tp(tot)) is ________
A 22-MHz clock signal is put into a MOD-16counter.
What is the frequency of the Q output of each stage of the counter
Q1 = 22 MHz, Q2 = 22 MHz, Q3 = 22 MHz, Q4 = 22 MHz
Q1 = 11 MHz, Q2 = 5.5 MHz, Q3 = 2.75 MHz, Q4 = 1.375 MHz
Q1 = 11 MHz, Q2 = 11 MHz, Q3 = 11 MHz, Q4 = 11 MHz
Q1 = 22 MHz, Q2 = 11 MHz, Q3 = 5.5 MHz, Q4 = 2.75 MHz
One of the major drawbacks to the use of asynchronous counters is
low-frequency applications are limited because of internal propagation delays
high-frequency applications are limited because of internal propagation delays
Which of the following is a type of shift register counter
List which pins need to be connected together on a 7492 to make a MOD-12 counter
1 to 12, 9 to 6, 8 to 7
1 to 12
1 to 12, 12 to 6, 11 to 7
1 to 12, 11 to 6, 9 to 7
List which pins need to be connected together on a 7493 to make a MOD-12 counter
12 to 1, 11 to 3, 8 to 2
12 to 1, 11 to 3, 12 to 2
12 to 1, 11 to 3, 9 to 2
12 to 1, 11 to 3, 1 to 2
The terminal count of a 3-bit binary counter in the DOWN mode is ________
A 12 MHz clock frequency is applied to a cascaded counter containing a modulus-5 counter, a modulus-8 counter, and a modulus-10counter.
The lowest output frequency possible is ________
Integrated-circuit counter chips are used in numerous applications including
data generation, counting operations, sequencing, and frequency multiplication
timing operations, counting operations, sequencing, and frequency multiplication
timing operations, decoding operations, sequencing, and frequency multiplication
timing operations, counting operations, sequencing, and frequency division
Three cascaded decade counters will divide the input frequency by ________
The designation means that the ________
up and down counts are both active-LOW
up count is active-HIGH, the down count is active-LOW
up and down counts are both active-HIGH
up count is active-LOW, the down count is active-HIGH
How many flip-flops are required to make a MOD-32 binary counter
Assume you want to determine the timing diagram for a 4-bit counter using anoscilloscope.
The best choice for an oscilloscope trigger signal is ________
the most significant bit (MSB)
from a composite of the MSB and LSB
the least significant bit (LSB)
the clock signal
A MOD-12 and a MOD-10 counter arecascaded.
Determine the output frequency if the input clock frequency is 60 MHz
How many different states does a 3-bit asynchronous counter have
Shift-register counters use ________, which means that the output of the last FF in the register is connected back to the first FF in some way
The circuit given below has no output on Q1 when examined with anoscilloscope.
All J-K inputs are HIGH, the CLK signal is present, and the Q0 istoggling.
The C input of FF1 is a constantLOW.
What could be causing the problem
Either the output of FF0 or the input of FF1 may be shorted to ground.
The input of FF1 may be shorted to ground.
The output of FF0 may be shorted to ground.
The Q0 output should be connected to the J input of FF1.
Using four cascaded counters with a total of 16 bits, how many states must be deleted to achieve a modulus of 50,000
What type of register is shown below
Parallel in/parallel out register
Serial in/parallel out register
Serial/parallel-in parallel-out register
Parallel-access shift register
The circuit shown below is used for ________, and for the inputs shown, the DATA output will be ________
parallel-to-serial conversion, HIGH
parallel-to-serial conversion, 0
MOD-6 and MOD-12 counters and multiples are most commonly used as
power consumption meters
Why can a synchronous counter operate at a higher frequency than a ripple counter
The flip-flops change at the same time.
The flip-flops change one after the other.
A synchronous counter cannot operate at higher frequencies.
A ripple counter is faster.
Three cascaded modulus-5 counters have an overall modulus of ________
The technique used by one-shots to respond to an edge rather than a level is called ________