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How many AND gates would be required to completely decode ALL the states of a MOD-64 counter, and how many inputs must each AND gate have
128 gates, 5 inputs to each gate
64 gates, 5 inputs to each gate
128 gates, 6 inputs to each gate
64 gates, 6 inputs to each gate
The circuit shown below is used for ________, and for the inputs shown, the DATA output will be ________
parallel-to-serial conversion, HIGH
parallel-to-serial conversion, 0
The given circuit is a(n) ________
two-bit asynchronous binary counter
three-bit synchronous binary counter
four-bit asynchronous binary counter
eight-bit asynchronous binary flip-flop
Which segments of a seven-segment display would be required to be active to display the decimal digit 2
a, b, c, d, e, and f
a, c, d, f, and g
a, b, d, e, and g
a, b, c, d, and g
List the state of each output pin of a 7447 if RBI = 0, LT = 1, A0 = 1, A1 = 0, A2 = 0, and A3 = 1
RBO = 0, a = 0, b = 0, c = 0, d = 1, e = 1, f = 0, g = 0
RBO = 0, a = 0, b = 0, c = 0, d = 0, e = 1, f = 0, g = 0
RBO = 1, a = 0, b = 0, c = 0, d = 0, e = 1, f = 0, g = 0
RBO = 1, a = 0, b = 0, c = 0, d = 1, e = 1, f = 0, g = 0
Referring to the given figure, at which point is the serial data transferred to the parallel output
The technique used by one-shots to respond to an edge rather than a level is called ________
Which of the following groups of logic devices would be the minimum required for a MOD-64 synchronous counter
Seven flip-flops, five AND gates
Five flip-flops, three AND gates
Six flip-flops, four AND gates
Four flip-flops, ten AND gates
List which pins need to be connected together on a 7493 to make a MOD-12 counter
12 to 1, 11 to 3, 9 to 2
12 to 1, 11 to 3, 1 to 2
12 to 1, 11 to 3, 12 to 2
12 to 1, 11 to 3, 8 to 2
A BCD counter is a ________
Select the response that best describes the use of the Master Reset on typical 4-bit binary counters
When MR1 and MR2 are both HIGH, all Qs will be reset to one.
MR1 and MR2 are provided to synchronously reset all four flip-flops.
To enable the count mode, MR1 and MR2 must be held LOW.
When MR1 and MR2 are both HIGH, all Qs will be reset to zero.
A seven-segment, common-anode LED display is designed for
one common LED
disorientation of segment modules
all cathodes to be wired together
a HIGH to turn off each segment
The hexadecimal equivalent of 15,536 is ________
The circuit given below fails to produce dataoutput.
The individual flip-flops are checked with a logic probe and pulser, and each checks OK. What could be causing the problem
One of the flip-flops may have a solder bridge between its input and Vcc.
One of the interconnect lines between two stages may have a solder bridge to ground.
The data output line may be grounded.
One of the clock input lines may be open.
The given circuit represents a(n) ________
four-bit binary counter
asynchronous BCD decade counter
synchronous BCD decade counter
A 5-bit asynchronous binary counter is made up of five flip-flops, each with a 12 ns propagationdelay.
The total propagation delay (tp(tot)) is ________
Which of the following is an invalid state in an 8421 BCD counter
An asynchronous 4-bit binary down counter changes from count 2 to count 3. How many transitional states are required
Which of the following is a type of shift register counter
The duty cycle of the most significant bit from a 4-bit (0–9) BCD counter is ________
How can a digital one-shot be implemented using HDL
By applying the concept of a counter
By applying a level trigger
By using a library function
By using a resistor and a capacitor
A BCD counter has ________ states
The terminal count of a modulus-11 binary counter is ________
Assume you want to determine the timing diagram for a 4-bit counter using anoscilloscope.
The best choice for an oscilloscope trigger signal is ________
from a composite of the MSB and LSB
the clock signal
the most significant bit (MSB)
the least significant bit (LSB)
A reliable method for eliminating decoder spikes is the technique called ________
Synchronous (parallel) counters eliminate the delay problems encountered with asynchronous (ripple) counters because the
input clock pulses are not used to activate any of the counter stages.
input clock pulses are applied only to the first and last stages.
input clock pulses are applied simultaneously to each stage.
input clock pulses are applied only to the last stage.
In general, when using a scope to troubleshoot digital systems the instrument should be triggered by ________
the system clock
the A channel or channel 1
line sync, in order to observe troublesome power line glitches
the vertical input mode, when using more than one channel
Which of the following is an example of a counter with a truncated modulus
The decimal equivalent of the largest number that can be stored in a 4-bit binary counter is ________
Shift-register counters use ________, which means that the output of the last FF in the register is connected back to the first FF in some way