Combinational Logic Circuits
The largest truth table that can be implemented directly with an 8-line-to-1-line MUX has ________
For a two-input XNOR gate, with the input waveforms as shown below, which output waveform is correct
Which of the circuits in figure
d) is the sum-of-products implementation of figure
A decoder can be used as a demultiplexer by ________
tying all data-select lines HIGH
tying all data-select lines LOW
tying all enable pins LOW
using the input lines for data selection and an enable line for data input
The design concept of using building blocks of circuits in a PLD program is called a(n)
A circuit that can convert one of ten numerical keys pressed on a keyboard to BCD is a ________
What is the indication of a short to ground in the output of a driving gate
The node may be stuck in either the HIGH or the LOW state.
There is a signal loss to all load gates.
Only the output of the defective gate is affected.
The affected node will be stuck in the HIGH state.
The AND-OR-INVERT gates are designed to simplify implementation of ________
Which of the following expressions is in the sum-of-products form
(a + b)(c + d)
AB + CD
As a technician you are confronted with a TTL circuit board containing dozens of ICchips.
You have taken several readings at numerous IC chips, but the readings are inconclusive because of their erraticnature.
Of the possible faults listed, select the one that most probably is causing the problem
A solar bridge between the inputs on the first IC chip on the board
A defective IC chip that is drawing excessive current from the power supply
A defective output IC chip that has an internal open to Vcc
An open input on the first IC chip on the board
Two 4-bit comparators are cascaded to form an 8-bitcomparator.
The cascading inputs of the most significant 4 bits should be connected ________
A = B to a logic high, A < b and a > B to a logic low
to the cascading inputs of the least significant 4-bit comparator
to the outputs from the least significant 4-bit comparator
Parity generators and checkers use ________ gates
Two 4-bit binary numbers
(1011 and 1111) are applied to a 4-bit paralleladder.
The carry input is 1. What are the values for the sum and carry output
4321 = 1011, Cout = 1
4321 = 1100, Cout = 1
4321 = 1111, Cout = 1
4321 = 0111, Cout = 0
How many 4-bit parallel adders would be required to add two binary numbers each representing decimal numbers up through 30010
The 7447A is a BCD-to-7-segment decoder with ripple blanking input and outputfunctions.
The purpose of these lines is to ________
turn off the display for any nonsignificant digit
test the display to assure all segments are operational
turn off the display for leading or trailing zeros
turn off the display for any zero
The implementation of simplified sum-of-products expressions may be easily implemented into actual logic circuits using all universal ________ gates with little or no increase in circuitcomplexity.
(Select the response for the blank space that will BEST make the statementtrue.
A Karnaugh map will ________
eliminate the need for tedious Boolean simplifications
give an overall picture of how the signals flow through the logic circuit
produce the simplest sum-of-products expression
allow any circuit to be implemented with just AND and OR gates
A logic probe is placed on the output of a gate and the display indicator isdim.
A pulser is used on each of the input terminals, but the output indication does notchange.
What is wrong
The dim indication is a result of a bad ground connection on the logic probe.
The dim indication on the logic probe indicates that the supply voltage is probably low.
The output of the gate appears to be open.
The gate may be a tristate device.
To subtract a signed number (the subtrahend) from another signed number (the minuend) in the 2's complement system, the minuend is ________
complemented only if it is negative
complemented only if it is positive
The output of a gate has an internal short; a current tracer will ________
show whether the gate is shorted to Vcc or ground
be able to identify the defective load node
identify the defective gate
probably not be able to locate the problem
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Practice mcqs on Combinational Logic Circuits
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Combinational Logic Circuits
Combinational Logic Analysis
MSI Logic Circuits
Describing Logic Circuits
Sequential Logic Circuits
Programmable Logic Device
Circuit Logic Families
Logic Families and Their Characteristics
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