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The circuit shown below is used for ________, and for the inputs shown, the DATA output will be ________
parallel-to-serial conversion, 0
parallel-to-serial conversion, HIGH
demultiplexing, 0
multiplexing, 1
What type of register is shown below
Parallel in/parallel out register
Serial in/parallel out register
Parallel-access shift register
Serial/parallel-in parallel-out register
In general, when using a scope to troubleshoot digital systems the instrument should be triggered by ________
the system clock
the A channel or channel 1
line sync, in order to observe troublesome power line glitches
the vertical input mode, when using more than one channel
A D flip-flop can be made to toggle by ________
Three cascaded decade counters will divide the input frequency by ________
100
1,000
10
20
A 4-bit ripple counter consists of flip-flops, which each have a propagation delay from clock to Q output of 15 ns. For the counter to recycle from 1111 to 0000, it takes a total of ________
45 ns
30 ns
15 ns
60 ns
Assume a 4-bit ripple counter has a failure in the second flip-flop such that it "locks up." The third and fourth stages will ________
turn into molten silicon
continue to count with correct outputs
stop counting
continue to count but have incorrect outputs
What is the difference between a 7490 and a 7493
7490 is a MOD-10, 7493 is a MOD-12
7490 is a MOD-16, 7493 is a MOD-10
7490 is a MOD-12, 7493 is a MOD-16
7490 is a MOD-10, 7493 is a MOD-16
An asynchronous binary up counter, made from a series of leading edge-triggered flip-flops, can be changed to a down counter by ________
taking the output on the other side of the flip-flops ( instead of Q)
clocking of each succeeding flip-flop from the other side ( instead of Q)
changing the flip-flops to trailing edge triggering
All of the above
A BCD counter has ________ states
10
11
9
8
Assume you want to determine the timing diagram for a 4-bit counter using anoscilloscope.
The best choice for an oscilloscope trigger signal is ________
the least significant bit (LSB)
the most significant bit (MSB)
the clock signal
from a composite of the MSB and LSB
A modulus-10 counter must have ________
synchronous clocking
10 flip-flops
flip-flops
2 flip-flops
How many different states does a 2-bit asynchronous counter have
8
2
4
1
The technique used by one-shots to respond to an edge rather than a level is called ________
level management
edge triggering
trigger input
edge trapping
A 12 MHz clock frequency is applied to a cascaded counter containing a modulus-5 counter, a modulus-8 counter, and a modulus-10counter.
The lowest output frequency possible is ________
60 kHz
30 kHz
10 kHz
20 kHz
In a VHDL retriggerable edge-triggered one-shot, which condition will not exist when a clock edge occurs
A trigger edge has occurred and we must load the counter.
The counter is zero and we need to keep it at zero.
The counter is not zero and we need to count down by one.
The shift register is reset.
What decimal value is required to produce an output at "X"
5
1
2
1 or 4
A MOD-16 ripple counter is holding the count10012.
What will the count be after 31 clock pulses
10112
10102
11012
10002
The given circuit represents a(n) ________
asynchronous BCD decade counter
BCD-to-decimal decoder
four-bit binary counter
synchronous BCD decade counter
Which of the following is an invalid output state for an 8421 BCD counter
0000
0001
1110
0010
1
2
3
6
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