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A binary-weighted-input digital-to-analog converter has a feedback resistor, Rf, of 12 k. If 50 A of current is through the resistor, voltage out of the circuit is ________
–0.6 V
0.6 V
0.1 V
–0.1 V
What is the result of taking more samples during the quantization process
More accurate signal representation
More bit requirements and more accurate signal representation
More errors in the analog-to-digital conversion
More bit requirements
Assume that in a certain 4-bit weighted ladder DAC, the input representing the most significant bit is applied to a 20 kresistor.
What is the size of the resistor that represents the least significant bit
160 K
2.5 K
80 k
5 k
The number of data lines on the GPIB is ________
1
8
4
16
The dual-slope analog-to-digital converter finds extensive use in ________
function generators
frequency counters
digital voltmeters
All of the above
Which A/D conversion method has a fixed conversion time
dual-slope analog-to-digital converter
digital-ramp analog-to-digital converter
single-slope analog-to-digital converter
successive-approximation analog-to-digital converter
The ADC0804 is an example of a ________
single-slope analog-to-digital converter
digital-ramp analog-to-digital converter
dual-slope analog-to-digital converter
successive-approximation analog-to-digital converter
The principal advantage of the three-wire handshake on the GPIB is that it ________
is faster than two-wire methods
allows fast and slow listeners on the same bus
is compatible with the RS232C standard
can be used over very long distances
An op-amp has very ________
High voltage gain
All of the above
high input impedance
low output impedance
If a DAC has a full-scale, or maximum, output of 12 V and accuracy of 0.1%, then the maximum error for any output voltage is ________
0 V
12 mV
12 V
120 mV
Which type of ADC quantizes the analog signal into a stream of bits whose amount corresponds to the signal level
Dual-slope
Successive approximation
None of the above
Sigma-delta
Which of the following best defines Nyquist frequency
The second harmonic
The lower frequency limit of sampling
The highest frequency component of a given analog signal
The frequency of resonance for the filtering circuit
A standard logic device can be connected on a bus system as an open-collector logic device by connecting each output to a ________
light-emitting diode
CMOS buffer
10 k series resistor
discrete transistor
For a 4-bit DAC, the least significant bit (LSB) is ________
0.625% of full scale
6.25% of full scale
12% of full scale
1.2% of full scale
An ADC that uses an up/down counter
(and other devices) to follow changes in the input analog signal is a ________
tracking converter
dual-slope ramp converter
single-slope ramp converter
successive-approximation converter
Of the methods listed, the fastest A/D conversion is done by a ________
dual-slope ramp converter
successive-approximation converter
single-slope ramp converter
tracking converter
A 4-bit R/2R ladder digital-to-analog converter uses ________
one resistor value
two resistor values
three resistor values
four resistor values
In a digital reproduction of an analog curve, accuracy can be increased by ________
sampling the curve less often
sampling the curve more often
decreasing the number of bits used to represent each sampled value
All of the above
Settling time is normally defined as the time it takes a DAC to settle within ________
1/4 LSB of its final value when a change occurs in the input code
1/2 LSB of its final value when a change occurs in the input code
1 LSB of its final value when a change occurs in the input code
1/8 LSB of its final value when a change occurs in the input code
Which term applies to the maintaining of a given signal level until the next sampling
Shannon frequency sampling
Aliasing
Holding
"Stair-stepping"
1
2
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