Digital System Projects Using HDL
In the frequency counter, the control clock is derived from the ________ by frequency dividers controlled in the control and timing block
system clock signal
In the digital clock project, when does the PM indicator go high
Going from 11:59:59 to 12:00:00
Going from 12:59:59 to 01:00:00
On the falling edge of the clock after enable goes high
In the digital clock project, the 1 pps signal is used as a synchronous clock for all of the counter stages, which are ________
advanced BCD counters
1 pulse per second
In the keypad encoder, the ________ activate(s) the freeze bit only when one column is low
How is the output frequency related to the sampling interval of a frequency counter
Less precision with longer sampling interval
Directly with the sampling interval
More precision with longer sampling interval
Inversely with the sampling interval
In the keypad encoder, the ________ must hold in its current state until a key is released
The interface of the stepper motor needs to operate in one of ________ mode(s)
The step rate of the simulation of a stepper motor is probably ________ the actual stepper motor
almost the same as
exactly the same as
Why should a real hardware functional test be performed on the HDL stepper motor design
To check the speed of the software
To check the current levels in the motor
To check the voltage levels of the real outputs
To provide a fully operational system
In the keypad application, what does the data signal define
The ring counter data
The freeze locator data
The row and column encoded data
The ring encoded data
Depending on the ________ the IC is in, the output of the stepper motor HDL will respond to each pulse by changing state
In the digital clock project, when it is 11:59:59, AND gate 1 detects that the tens of hours is 1 and the enable input isactive.
On the next clock pulse the AM/PM flip-flop will ________
In the digital clock project, the purpose of the frequency prescaler is to
allow the BCD display to have a value from 00–59.
transform a 60 pps input to a 1 pps timing signal.
find the basic frequency.
prevent the clock from exceeding 12:59:59.
Using one case construct inside another is known as ________
In the keypad encoder, just after the 4 ms mark, the simulation initiates the release of the key by changing the column value to ________, which causes the d output to go into its Hi-Z state
Which is not a step in strategic planning for HDL development
The exact operation of each block must be thoroughly defined and understood.
The names of each input and output must be known.
There must be a way to test each piece.
Each block must fit together to make up the whole system.
In the digital clock project, what type of counter is used to count to 59 seconds
BCD followed by a MOD-6
In the digital clock project HDL code, the MOD-12 counter is using ________
a MOD-12 counter followed by a D flip-flop
a single HDL module
a BCD counter followed by a MOD-2 counter
a MOD-6 counter followed by a MOD-2 counter
Which is not a step used to define the scope of an HDL project
A clear vision of how to make each block work
What are the speed requirements?
How many bits of data are needed?
Are the inputs and outputs active HIGH or active LOW?
When designing an HDL digital system, which is the worst mistake one can make
Failing to provide proper documentation
Concluding that a fundamental block works perfectly
Overlooking a possible VARIABLE
Adding blocks of code prior to testing them
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