A gated S-R flip-flop goes into the CLEAR condition when ________
S is LOW; R is HIGH; EN is LOW
S is HIGH; R is LOW; EN is LOW
S is LOW; R is HIGH; EN is HIGH
S is HIGH; R is LOW; EN is HIGH
The circuit that is primarily responsible for certain flip-flops to be designated as edge-triggered is the
A gated S-R flip-flop is in the hold condition whenever ________
the Gate Enable is HIGH and the S and R inputs are both LOW
the Gate Enable is LOW
the S and R inputs are both LOW
the Gate Enable is HIGH
The 74121 nonretriggerable multivibrator can have the output pulse set by a single externalcomponent.
This component is a(n) ________
An RC circuit used in a 74122 retriggerable one-shot has an REXT of 100 k and a CEXT of 0.005 F. The pulse width is ________
How is a J-K flip-flop made to toggle
J = 0, K = 0
J = 1, K = 1
J = 1, K = 0
J = 0, K = 1
With four J-K flip-flops wired as an asynchronous counter, the first output change of divider #4 indicates a count of how many input clock pulses
A D flip-flop utilizing a PGT clock is in the CLEARstate.
Which of the following input actions will cause it to change states
CLK = PGT, D = 0
CLK = NGT, D = 0
CLK = NGT, D = 0, CLOCK NGT, D = 1
CLOCK PGT, D = 1
CLOCK NGT, D = 1
The advantage of a J-K flip-flop over an S-R FF is that ________
it has no invalid states
it has only one output
it has fewer gates
it does not require a clock input
The toggle mode is the mode in which a(n) ________ changes states for each clock pulse
With regard to a D latch, ________
the Q output follows the D input when EN is HIGH
the Q output is HIGH regardless of EN's input state
the Q output is opposite the D input when EN is LOW
the Q output follows the D input when EN is LOW
The output pulse width of a 555 monostable circuit with R1 = 4.7 k and C1 = 47 F is ________
Which statement BEST describes the operation of a negative-edge-triggered D flip-flop
The Q output is ALWAYS identical to the D input.
The Q output is ALWAYS identical to the CLK input if the D input is HIGH.
The Q output is ALWAYS identical to the D input when CLK = PGT.
The logic level at the D input is transferred to Q on NGT of CLK.
The phenomenon of interpreting unwanted signals on J and K while Cp
(clock pulse) is HIGH is called ________
parity error checking
A correct output is achieved from a master-slave J-K flip-flop only if its inputs are stable while the
flip-flop is reset
clock is HIGH
slave is transferring
clock is LOW
A positive edge-triggered D flip-flop will store a 1 when ________
the D input is HIGH and the clock transitions from LOW to HIGH
the D input is HIGH and the clock is HIGH
the D input is HIGH and the clock is LOW
the D input is HIGH and the clock transitions from HIGH to LOW
What is the hold condition of a flip-flop
only S is active
both S and R inputs activated
no active S or R input
only R is active
The circuit given below fails to function; the inputs are checked with a logic probe and the following indications are obtained: CLK, J1, J2, J3, K1, K2, and K3 arepulsing.
Q and areHIGH.
and PRE areLOW.
What could be causing the problem
The PRE is stuck LOW.
There is no problem.
The clock should be held HIGH.
The CLR is stuck HIGH.
In VHDL, how is each instance of a component addressed
A name followed by a semicolon and the component type
A name followed by the library being used
A name followed by a colon and the name of the library primitive
A name followed by the component library number
The key to edge-triggered sequential circuits in VHDL is the ________
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Practice mcqs on Flops
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Flops and Timers
D Flip Flops
CMOS implementation of SR Flip Flops
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